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What is the timing of a flip-flop

Consider an edge-triggered D-type flip-flop. In this example we are considering a positive-edge triggered or rising-edge triggered flip-flop.

On the rising edge of the clock trace (change from zero to one - low to high voltage), the input D is sampled and transferred to the output, Q. At all other times the state of D is ignored.

Although the time interval for that rise from state 0 to state 1 looks as if it is zero one a graph, in reality it is a small time period. During that tiny time period the state of D must be stable. In fact the state of D must be stable for a short time before and after the clock signal rises.

Look at the diagram above. You will see that the transfer of the D state to Q is a small (but measurable) time interval after the clocked event.

The diagram below shows the time delays involved in data transfer on a scale that makes them easier to see.

 

Clock (CLK) - steady square wave that synchronizes the system

D - data signal from which input is sampled

Q - data output signal


Timing Terms

Setup Time - period of time when the input must be stable before the rising edge of the CLK
Hold Time - period of time when the input must be stable after the rising edge of the CLK
“CLK-to-Q” Delay - how long it takes the output to change, measured from the rising edge of the CLK